As smaller transistors are manufactured, the critical dimension (CD) or resolution of patterned features is becoming more challenging to produce. Sub 10 nm technology nodes require stringent thickness, uniformity and almost no margin or variation at the atomic level to design specifications. Self-aligned patterning needs to replace overlay-driven patterning so that cost-effective scaling can continue even after EUV introduction. Selective etching and deposition of thin films is a key step in patterning highly scaled technology nodes.